Ripple-carry adder

ABSTRACT

An adder cell for a ripple-carry adder, suitable for use in an integrated circuit employing CMOS technology, has a gate arrangement for two input variables and a carry input signal, with outputs for sum and carry signals, in accordance with the signals presented to the inputs. The gate arrangement is arranged so that the charging of the capacitance of the carry output takes place from a supply voltage through two transistor gates, not contained in a combination gate, so that one of the transistor gates may be formed as a driving inverter separate from the time-critical carry-propogation path, and designed with significantly lower impedance than the other transistor gates. Alternatively, a single transistor gate is employed for charging the capacitance of the carry output directly form a supply voltage.

RELATED APPLICATION

A related application is Knauer Application Ser. No. 902,641, filedSept. 2, 1986.

BACKGROUND

The present invention relates to an adder cell for a ripple-carry adderand more particularly to such a cell which may be executed in CMOStechnology as an integrated circuit.

Adders are required in a large number of digital logic circuits, forexample in digital filters, signal processors, and microprocessors. Aprinciple for such an adder is the ripple-carry method, in which a carrysignal is serially transmitted from an adder cell for a lower-order bitto the adder cell for the next higher order bit. The addition time isdefined essentially by the time required for the carry propagation. Moreinvolved adder arrangements such as, for example, the look-ahead carrymethod are based on the ripple-carry method.

Ripple-carry adder cells are known, for example, from H. Weiss, K.Horninger, "Intergrierte MOS-Schaltungen", Springer-Verlag,Berlin-Heidelberg, New York (1982), pp. 188-194. Such adders cells areaffected by the disadvantage that the carry path, which is a criticaldeterminant of overall computing time of an arithmetic unit constructedwith such cells, either has a relatively large number of seriallyconnected gates, or else the gates are components of combination gates.In the former case, the large number of serially connected gates has anunfavorable effect on the propagation time of carry signals. In thesecond case, there may be the additionally unfavorable fact that thecharging of the capacitance of the carry output does not take place withthe required edge steepness, due to the relatively high impedance of thegates fashioned as component parts of combination gates.

BRIEF DESCRIPTION OF THE INVENTION

A principal object of the present invention is to provide an adder cellof the ripple-carry type, in which the disadvantages of known addercells are effectively avoided and in which the circuit complexity isconsiderably reduced so that less space is required for an integratedcircuit incorporating the adder cell.

This object is realized in the present invention by an an adder cellhaving a gate arrangement such that the capacitance of the carry outputis charged through two transistor gates which are not contained in acombination gate so that one of the gates can be designed withsignificant lower-impedance, without limitation due to the geometry ofthe integrated circuit containing such cell.

In another arrangement, this object is attained by employing a singletransistor for charging the capacitance of the carry output which is notcontained in a combination gate go that it can be designed withsignificantly lower-impedance.

These and other objects and advantages of the present inventon willbecome manifest by an inspection of the following description and theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

Reference will now be made to the accompanying drawings in which:

FIG. 1 is a schematic diagram of a first exemplary embodiment of thepresent invention; and

FIG. 2 is a schematic diagram of a second exemplary embodiment of thepresent invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring to FIG. 1, the adder cell in accordance with a first exemplaryembodiment of the invention incorporates a gate arrangement for twovariables identified as A and B, with a carry input C_(in), and with sumand carry output terminals S and C_(out).

Two input terminals for the variables A and B are respectively connectedto inputs of a first NAND gate 1 and to a NOR gate 2. The output of theNAND gate 1 is connected to the input of a single transistor gate 3,acting as an inverter, and to one input of a further NAND gate 5. Theoutput of the NOR gate 2 is connected to the input of another transistorgate 4 acting as an inverter. The output of the gate 3 is connected tothe source electrode of the single transistor gate 7, shown as ap-channel FET, and acting as a transfer gate. The output of gate 4acting as an inverter is connected to the source electrode of anothertransistor gate 8, shown as an n-channel FET and acting as a transfergate. The output of the gate 4 is also connected to a second input ofthe NAND gate 5.

The drain electrodes of the two transistor gates 7, 8 are connected incommon to the output terminal for the carry output C_(out). The outputof the NAND gate 5 is connected to the source electrode of a furthertransistor gate 9 shown as an nchannel FET and acting as a transfergate. The output of the NAND gate 5 is also connected to the input of afurther transistor gate 6 acting as an inverter and this output isconnected to the source electrode of a further transistor gate 10, shownas a p-channel FET and acting as a transfer gate. The drain electrodesof the two transistor gates 9 and 10 are connected in common to theoutput terminal for the sum signal S. The gate electrodes of all of thetransistor gates 7-10 are connected in common to the input terminal forthe carry input signal C_(in).

In the arrangement of FIG. 1, the charging of the capacitance of thecarry output at the outputs of the gates 7 and 8 proceeds from a supplyvoltage source through the series connected gates 3 and 7, or the seriesconnected gates 4 and 8. The gates 3 and 4 are formed as drivinginverters and are not inserted in the time-critical carry propagationpath. These driving inverters can be designed with significantlylower-impedance than the transistor gates 7 and 8, and can be designedlarger in size, without restriction due to the layout geometry, becausethey are not in the time critical carry path. This enables a circuit ofFIG. 1 to achieve a significantly faster carry propagation.

The circuit of FIG. 1 requires only 22 transistors, which is aconsiderable savings in comparison to 28 transistors typically used inconventional adder cells. Similar to conventional designs, the carryoutput is supplied via a series connection of two transistors. Howeverin the apparatus of FIG. 1, contrary to previous designs, the seriesconnected gates are not contained in a combination gate. Thus, thedriving inverters, not within the time-critical carry path, can bedesigned with substantially lower-impedance than the following transfergates 7 and 8, without encountering any difficulties in layout geometryof an integrated circuit incorporating the adder cell. Essentially fourtransistor gates affect charging of the load capacitance, correspondingto a conventional adder cell incorporating 28 transistors.

The arrangement of FIG. 1 is particularly well suited for adders havingonly a few adder cells (for example two). When a large number of addercells is employed, there is a potential for incorrect operation, sincethe threshold voltages of the transistors in the carry path arecumulative. This disadvantage is overcome with the arrangement of FIG.2.

In FIG. 2 the input terminals for the two variables A and B arerespectively connected to inputs of a first NAND gate 1 and of a NORgate 2. The output of NAND gate 1 is connected to the source electrodeof a first transistor gate 7, shown as a p-channel FET and acting as atransfer gate. The output of the NAND gate 1 is also connected to oneinput of a further NAND gate 5.

The output of the NOR gate 2 is connected to the source electrode of atransistor gate 8 shown as an n-channel FET and acting as a transfergate. The output of the NOR gate 2 is also connected to the input of afurther transistor gate 3', which acts as inverter. The output of thegate 3' is connected to the second input of the NAND gate 5. The outputof the NAND gate 5 is connected to the source electrode of a thirdtransistor gate 9, shown as a n-channel FET and acting as a transfergate, and is also connected to the input of a further transistor gate 6acting as an inverter. The output of the gate 6 is connected to thesource electrode of a fourth transistor gate 10 shown as a p-channel FETand acting as a transfer gate. The drain electrodes of the transistorgates 7 and 8 are connected in common to the input of a transistor gate4', acting as a driving inverter. The output of the gate 4' is connectedto the output terminal for the carry output C_(out). The drainelectrodes of the transistor gates 9 and 10 are connected to the outputterminal for the sum signal S. The gate electrodes of all transistorgates 7-10 are connected in common to the input terminal for the carryinput signal C_(in).

In the arrangement of FIG. 2, the voltage drop caused by the thresholdvoltages of the transistors, noted above in connection with FIG. 1, iseliminated, by the inverter 4' which is inserted into the carry path,such inverter not being a component part of a combination gate andtherefore being capable of being designed with lower-impedance. Thedesign of the inverter 4' is also free of difficulties with respect tolayout geometry. Due to its low-impedance, a fast charging of thecapacitance of the output carry is produced, up to its maximum voltage.

The arrangement of FIG. 2 comprises a gate arrangement in which thecharging of the capacitance of the carry output takes place over asingle transistor gate 4', proceeding from a supply voltage source. Thearrangement of FIG. 2, like that of FIG. 1, requires only 22 transistorsin comparison with the 28 transistors used in previous arrangements.Therefore, the circuits of the present invention require less space whenembodied in integrated circuit designs.

It is apparent that various modifications and additions may be made inthe apparatus of the present invention, without departing from theessential features of novelty thereof, which are intended to be definedand secured in the appended claims. For example, the gate arrangementsof the two described embodiments may be modified in accordance with therules of Boolean algebra.

What is claimed is:
 1. An adder cell for a ripple-carry adder suitablefor complementary metal oxide semiconductor technology and having outputcapacitance, said adder cell has a voltage supply and comprising a gatearrangement for accepting two input variables and an input carry signal,and for supplying sum and carry output signals to a pair of sum andcarry output terminals, in accordance with said inputs, said gatearrangement establishing a carry propagation path connecting said carryinput signal to said carry output terminal, said gate arrangementcomprising, in combination, first and second transistor gates connectedin series, with the output of said first gate connected to the input ofsaid second gate and the output of said second gate being connected tosaid carry output terminal, whereby the output capacitance of said addercell is charged from said voltage supply through said two transistorgates, both of said first and second transistor gates having a singledata input, said first transistor gate comprising a driving inverter notin series with said carry propagation path, and having a lower impedancethan said second gate, whereby the size of said first gate is notaffected by the layout geometry of said adder cell in an integratedcircuit, and means for connecting said second gate to receive said inputcarrying signal.
 2. An adder cell according to claim 1, wherein saidgate arrangement includes a first NAND gate having inputs connected toreceive said two input variables, a NOR gate having inputs connected toreceive said two input variables, a first inverter, means for connectingthe output of said first NAND gate to the input of said first inverter,a second NAND gate, means for connecting the output of said first NANDgate to a first input of said second NAND gate, a second inverter, meansfor connecting the output of said NOR gate to the input of said secondinverter, a first transfer gate comprising a p-channel field effecttransistor (FET) having its source electrode connected to the output ofsaid first inverter, a second transfer gate comprising an n-channel FETand having its source electrode connecting to the output of said secondinverter, means connecting a second input of said second NAND gate tothe output of said second inverter, means for connecting the drainelectrodes of said two transfer gate to a terminal for manifesting thecarry output signal, a third transfer gate comprising an n-channel FEThaving its source electrode connected to the output of said second NANDgate, a fourth transfer gate comprising a p-channel FET having itssource electrode connected to the output of said second NAND gatethrough a third inverter, means for connecting the drain electrodes ofsaid third and fourth transfer gates to a terminal for manifesting thesum output signal, and means for connecting the gate electrodes of allof said transfer gates to receive the input carry signal.
 3. Anintegrated circuit incorporating an adder cell for a ripple-carry addersuitable for complementary metal oxide semiconductor technologycomprising, said adder cell a gate arrangement with a plurality of gatesfor accepting two input variables and an input carry signal and forsupplying sum and carry sum and carry output signals to a pair of outputterminals in accordance with said inputs, said gate arrangement havingtwo carry propagation paths, each comprising, in combination, asingle-transistor gate having its output connected to said carry outputterminal to charge the capacitance of said carry output terminal from avoltage supply, said single-transistor gate having a single data input,said single-transistor gate having a lower impedance than other gates ofsaid plurality of gates in said gate arrangement, whereby the size ofsaid singletransistor gate is not affected by the layout geometry ofsaid adder cell in an integrated circuit.
 4. An adder cell according toclaim 3, wherein said gate arrangement includes a first NAND gate havinginputs connected to receive said two input variables, a NOR gate havinginputs connected to receive said two input variables, a first transfergate comprising a p-channel field effect transistor (FET) having itssource electrode connected to the output of said first NAND gate, asecond transfer gate comprising an n-channel FET having its sourceelectrode connected to the output of said NOR gate, means for connectingthe drain electrodes of both of said first and second transfer gates tothe input of said single-transistor gate, a second NAND gate having oneinput connected to the output of said first NAND gate and the otherinput connected to the output of said NOR gate through an inverter, athird transfer gate comprising an n-channel FET having its sourceelectrode connected to the output of said second NAND gate, a fourthtransfer gate comprising a p-channel FET having its source electrodeconnected to the output of said second NAND gate through an inverter,means for connecting the drain electrodes of said third and fourthtransfer gates to the sum output terminal, and means for connecting thegate electrodes of all of said transfer gates in common to receive saidinput carry signal.